Impedance mismatch between transmission lines and driver/receiver impedances can cause signal reflections and may degrade the signal. One solution to the problem of mismatch between transmission lines and driver/receiver impedances has been to add a programmable impedance matching circuit to an input/output (I/O) buffer between the transmitter or receiver and the transmission line. The circuit includes an external resistor (RQ), a variable impedance sense control block, and an on-die pull-up (PU) array and pull-down (PD) array impedances (not shown) in the I/O buffers. The I/O buffer impedance is controlled by a digital code generated by the variable impedance sense control block. Generally, the variable impedance sense control block senses the mismatch between the on- and off-chip resistances then generates a code for the I/O buffers which minimizes the mismatch. The code updates are transmitted directly from the variable impedance sense control block to the I/O buffers.
Although this is an improvement over the prior buffers that lacked dynamic impedance matching circuits, the above approach is not wholly satisfactory for a number of reasons. One disadvantage with the above approach is all buffers may not see dynamic updates to the variable impedance sense code simultaneously due to propagation delays. The conventional approach for variable impedance sense code update timing is shown in FIG. 1. The variable impedance sense (VIS) control block 10 generates pull-up and pull-down codes to match the off-chip resistor 12 and the I/O buffers impedances. As the code changes, those changes propagate directly from the variable impedance sense control block 10 to all the I/O buffers 14, 16, 18.
The code updates arise from processes that are slow compared to the clock 20 and data 22, 24 frequencies, such as changes in impedance due to on-chip thermal variations. The code updates will therefore often consist of a change in the finest resolution made available by the code bits. If an increment (or decrement) of the code by such a resolution requires the combination of an increment (or decrement) or a larger resolution and a decrement (or increment) of another resolution (e.g., +0.25=−0.75+1), and if the different parts of this combination of changes can occur in a different order for different output buffers, and if the output buffers are transitioning when some but not all of the different parts of the combination of changes have occurred, the skew is introduced between the clock and data line.
The timing waveforms in FIG. 2 illustrate the worst case situation that may arise. In this example, the two “fraction bits” 26, 28 control one half of a leg (bit 1) 30 and one quarter of a leg (bit 0) 32, while the “integral bits” 34, 36 control entire legs. In this example the update consists of a quarter-leg increase, implement by a decrease of 0.75 legs, combined with an increase in one leg of the pull-up or pull-down array. The clock 20 and data 22 transitions occur part way through the update, with the data buffers only receiving the 0.75 leg decrease and the clock buffer only receiving the one leg increase. A 1.75 leg impedance mismatch ensues, which introduces skew 38.
Thus there exists a need for a circuit and method of dynamically updating the variable impedance sense code to the I/O buffers that improves accuracy and minimizes the worst case clock-to-data skew that may be induced by this update.